Intern - QEM PQE Wafer Level Reliability

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

• Location: 1 N Coast Dr, Fab10N, Singapore​

• Department: Quality Engineering Management (QEM) Product Quality Engineering (PQE)​

• Project Title: Cell Wafer Level Reliability (cWLR) System Metrics Shift Left through Test Optimization and Machine Learning​

• Description: Cell Wafer Level Reliability (cWLR) is critical in semiconductor wafer Fab for fast speed cell intrinsic reliability assessment including process conversion, device trim evaluation and Outgoing Quality Reliability Monitoring (OQRM) including endurance, high temperature/low temperature retention, read disturb, x-temperature metrics assessment. During the internship, you will work on project to future shift left system metrics to wafer level proxy metrics including trigger rate, RBER, HRER through test optimization and further apply Machine Learning (ML) models to realize a way of smart sampling to predict intrinsic reliability performance at High Volume Manufacturing (HVM) phase through constructing a faster, more effective and high-scalability intrinsic issue detection methodology to guard band the production line.​

• Scope: In this project, the student will​

• Learn the most advanced NAND cell wafer level reliability testing flow and method​

• Understand semiconductor reliability failure mechanisms and device physics​

• Partner with cross-site/cross-functional teams to develop and implement cWLR test program with shift-left initiatives​

• Learn NAND product characterization, experimentation and analysis to develop cWLR solutions for product issues​

• Learn Machine Learning modeling knowledge to predict NAND cell intrinsic reliability performance​

• Deliverable: To be able to understand semiconductor NAND memory functions and operations, probe and cWLR testing, develop shift-left reliability testing solutions, learn and apply machine-learning knowledge to develop predictive model for cell intrinsic reliability performance. ​

• Skillset Require: Python​

• Course of interests: Bachelor's/Master's Degree in Electrical/Electronic Engineering, Microelectronic is preferred​

• Duration Period: min 3 months​

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_sg@micron.com

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.