Modeling and simulation engineer for next generation computing architectures H/F

General information

Organisation

The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :
• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.

Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.

The CEA is established in ten centers spread throughout France
  

Reference

2025-35613  

Division description

The CEA's technology research division (DRT) develop a broad portfolio of technologies in the fields of information and communication, energy and health.
CEA technology research division leverages a unique innovation-driven culture and unrivalled expertise to develop and disseminate new technologies for industry, effectively bridging the gap between the worlds of research and industry. CEA-List is a research institute specialized in smart digital systems, located in the heart of the Paris-Saclay science and technology cluster.

Description de l'unité

Within CEA List, the EDA and Architectures Laboratory (LECA) develops innovative and flexible computing architectures that meet performance, cost, energy consumption, safety, and security requirements. To shorten development time and improve the quality of these architectures, the laboratory stands out by conducting cutting-edge research on innovative design tools and methods.

Position description

Category

Information system

Contract

Fixed-term contract

Job title

Modeling and simulation engineer for next generation computing architectures H/F

Socio-professional category

Executive

Contract duration (months)

18

Job description

As part of a multidisciplinary research team of experts in hardware IP design and design tools, you will contribute to the specification of modeling mechanisms / services and the (cloud-based) implementation of associated tools. Your primary task will be the implementation of SystemC virtual platforms and simulations for the architectural exploration thanks to CEA automated design space exploration framework for computing architectures (A-DECA). You will use and contribute to CEA Virtual Prototyping Simulation environment (VPSim) evolution.

In the context of HW architecture simulation and exploration, the laboratory develops virtual prototyping and architecture exploration tools. These tools integrate HW architecture modeling capabilities and executing binary software to be ported directly to a real target, as well as functional validation, debugging and performance evaluation of software in a fully virtualized environment. Integrating a large IP portfolio, it is possible to emulate functionality through QEMU (an extremely fast emulator that offers a wide range of advanced features for users and developers) and interfaces to use external models and obtain its performance data. Finally, a Python API describing the specific hardware platform to be simulated and the configuration parameters provides the ability to obtain the performance data of the simulated environment during the execution of applications for architecture exploration purposes.

You will join the research team of experts with the mission to contribute to the development of virtual prototype of computing platforms for simulation and design space exploration.

To perform your mission, you will be required to :

- Model and simulate a safety-relevant HW platform, potentially including simulation and modeling in the areas of real-time performance, shared memory access, virtualization, Service-Oriented Architecture (SoA), and safety-relevant topics;

- Collaborate with cross-functional teams to define and implement simulation and modeling activities;

- Develop and use CEA tools to perform multi-criteria performance analysis (mainly power, latency, and safety).

- Contribute to the scientific dissemination of the team's research results (contributions to publications in national and international conferences), design of videos, demonstrations, and tutorials as well as in the valorization of our innovations (writing of patents) To carry out your mission, you will have access to the laboratory's simulation, modeling and exploration tools.

Applicant Profile

You have an engineering/master's degree or a PhD in the field of electronics or embedded systems.

Required skills/knowledge:

- HW description languages: SystemC, VHDL, Verilog, SystemVerilog, CHISEL

- High level programming language: C++/Java/Scala ...

- Scripting languages : Bash/Python ...

- Development tools : IDE, make/cmake, svn/git, continuous integration, docker ...

- You understand HW constraints and have basic knowledge in industrial CAD tools (synthesis, verification, power analysis).

Desired experience and/or skills:

- Knowledge of digital electronic architecture (processors, Caches, NoC, ...) ;

- Experience in simulation/emulation, especially with QEMU

- Knowledge in Linux kernel development;

- Experience in other scripting languages (bash, tcl) would be a plus.

- Knowledge in the field of operational research and/or machine learning algorithms would be a plus.

Position location

Site

Saclay

Job location

France, Ile-de-France, Essonne (91)

Location

Saclay

Candidate criteria

Languages

• English (Fluent)
• French (Fluent)

Recommended training

Master degree, engineering degree or PhD in electronics or equivalent

Requester

Position start date

02/06/2025