Sr. Member of Technical Staff (Design Verification Engineer)

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.  

Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services.

Cerebras Systems Inc. has multiple openings for Sr. Member of Technical Staff (Design Verification Engineer)

Job Duties

• Develop test plans, create and maintain test components in SystemVerilog and UVM, collaborate with design engineers, automate regression testing, and debug test runs.
• Write detailed testbench functional specifications that document the components needed, such as drivers, monitors, protocol checkers, and scoreboards, while applying knowledge of UVM hardware verification methodology.
• Create test plans for hardware designs by studying the functional specifications and applying knowledge of complex protocols, such as PCIe.
• Research, evaluate, and recommend testbench components and test libraries that may be licensed from other companies.
• Design and develop the testbench components and environments using SystemVerilog, UVM, and C/C++.
• Implement tests using UVM sequences and SystemVerilog’s constrained random stimulus capabilities.
• Develop and maintain reference models based on functional specifications.
• Using a simulator, run tests on the testbench, including the reference model and design, and debug test failures using tools such as waveform viewers.
• Collaborate with hardware design engineers and system software engineers to review specifications and to recommend changes that will improve the quality and verifiability of the hardware designs.
• Create and maintain automated regression test scripts, using Python and/or Bash, that ensure that all hardware verification tests are run and pass after each change to the design, testbench, tests, or reference model.
• Analyze code and functional coverage results to find omissions in the test plans and/or defects in the implementation of the tests or the associated hardware components.
• Update knowledge and skills to keep up with rapid advancements in computer technology, design verification methodologies, and verification tools.

Minimum Requirements 

• Master’s degree or foreign equivalent degree in Computer Engineering, Electrical Engineering, or a related field and 3 years of experience as MTS Silicon Design Engineer, ASIC Engineer 3, Sr. Member of Technical Staff (Design Verification Engineer), Hardware Engineer, or a related occupation required. Employer accepts full-time or equivalent part-time experience.

The required work experience must include 2 years of experience with the following

• Defining and implementing verification methodologies and tests using SystemVerilog and C/C++, focusing on reusability and portability within the Universal Verification Methodology (UVM) test environment;
• Writing detailed testbench specifications, including documentation for drivers, monitors, protocol checkers, and scoreboards, applying knowledge of UVM verification methodology;
• Implementation of tests using UVM sequences and SystemVerilog constrained random stimulus capabilities;
• Running complex simulations and debugging simulation failures in Synopsys Verdi; and
• Analysis of functional coverage in SystemVerilog code to find omissions in the test plans and defects in the implementation of the tests.

Additional Information

• Employer’s Name: Cerebras Systems Inc.
• Job site: 1237 E Arques Ave, Sunnyvale, CA 94085
• Telecommuting permitted.
• Salary Range: $240,000.00 per year to $280,000.00 per year

If you are interested in applying for this position, please apply online on this web page or mail resume to HR at Cerebras Systems Inc., 1237 E Arques Avenue, Sunnyvale, CA 94085. Please reference Job # 139 on resume or cover letter.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection  point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

1. Build a breakthrough AI platform beyond the constraints of the GPU.
2. Publish and open source their cutting-edge AI research.
3. Work on one of the fastest AI supercomputers in the world.
4. Enjoy job stability with startup vitality.
5. Our simple, non-corporate work culture that respects individual beliefs.

Read our blog: Five Reasons to Join Cerebras in 2025.

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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