Senior Custom Circuit Architect

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Job Summary

We are seeking a highly experienced Senior Custom Circuit Architect with a Ph.D. in Electrical Engineering or related field and 5–7 years of hands-on industry experience in custom digital circuit design. The ideal candidate will have deep expertise in floating point arithmetic unit design at the schematic, gate, and layout levels, with a strong focus on transistor-level optimization, netlist refinement, and layout-aware tuning for advanced technology nodes.

Key responsibilities

• Architect and implement custom schematic-level designs for floating point datapaths, including adders, multipliers, dividers, normalization, rounding, and exception logic.

• Drive transistor- and gate-level design optimization to meet aggressive targets for power, performance, and area (PPA).

• Collaborate with layout engineers to ensure schematic-to-layout correlation and perform layout-driven circuit optimizations.

• Analyze post-layout parasitics and conduct SPICE/BSIM simulations to validate design robustness across PVT corners.

• Tune gate-level netlists using techniques such as logical effort, buffer insertion, sizing, and cell selection.

• Contribute to design methodology, custom cell integration, and physical verification signoff processes.

• Work closely with architecture, timing, and methodology teams to achieve best-in-class FPU implementations.

You may be a good fit if you have

• A Ph.D. in Electrical Engineering, Computer Engineering, or a related field with a focus on VLSI circuit design or microarchitecture.

• 5–7 years of industry experience in custom digital circuit design, especially in arithmetic-intensive blocks.

• A proven track record in designing and optimizing floating point math units at the schematic/gate level.

• Strong proficiency with tools such as Cadence Virtuoso, Synopsys Custom Compiler, Spectre, HSPICE, and FastSPICE.

• Deep knowledge of standard cell libraries, logical effort, transistor sizing, and layout parasitic impacts.

• Expertise in circuit reliability, signal integrity, and PVT corner analysis.

• Hands-on experience at advanced technology nodes (e.g., 5nm or below).

Strong candidates may also have experience with

• Published work or patents in the area of floating point or arithmetic logic design.

• Creating or customizing standard or leaf cells for specialized datapath logic.

• Power-aware design techniques, including body biasing or near-threshold voltage optimization.

• Scripting skills (Python, Perl, TCL) for design automation and verification workflows.

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered

• Housing subsidy of $2,000/month for those living within walking distance of the office

• Daily lunch and dinner in our office

• Relocation support for those moving to West San Jose

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.