Senior Timing and VF Methodology Engineer

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and SoCs. In this role, you’ll optimize performance, yield, and reliability by advancing modeling, analysis, and automation methods. Your work will affect products across AI, graphics, and autonomous vehicles. We're looking for someone passionate about the challenges of deep sub-micron design (3nm and beyond) who thrives on pushing the limits of precision and scalability. You’ll collaborate across teams to shape methodologies that influence the entire future of computing.

What you will be doing:

• Develop methodologies to bridge the gap between pre-silicon and post-silicon data VF and Vmin.

• Develop automation to scale V-F curve prediction across multiple projects covering CPUs and GPUs

• Collaborate with methodology leads, and timing engineers to refine silicon V-F projections to model sub-micron process effects

• Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.

• Work on various aspects of timing analysis and optimization with the goal of achieving best PPA

What We Need To See:

• MS (or equivalent experience) in Electrical or Computer Engineering with 3+ years’ experience in ASIC Design and Timing.

• Knowledge of device physics, STA methodology.

• Good understanding of mathematics/physics fundamentals of electrical design.

• Exposure to PrimeTime and timing closure derating methodologies

• Understanding crosstalk, electro-migration, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.

• Understanding of standard cells/memory/IO IP modeling and its usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.

• Expertise in coding- TCL, Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.

• Strong communications skill and good standout colleague

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

The base salary range is 168,000 USD - 310,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.