PCB Signal Integrity Validation Engineer

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Job Summary

Etched is seeking a skilled and driven Signal Integrity (SI) Validation Engineer to join our Platform team. This role is critical in ensuring our high-speed systems meet the most rigorous performance and reliability standards. The ideal candidate will focus on PCB-level validation of high-speed interfaces, with particular emphasis on >100GHz SerDes, PCIe Gen5/Gen6, and advanced signal integrity techniques. You’ll be responsible for validating power and signal margins, identifying SI bottlenecks, and ensuring robust performance through precision lab measurements and analysis.

Key responsibilities

• High-Speed Interface Validation: Characterize and validate high-speed interfaces such as >100GHz SerDes, PCIe Gen5/6, ensuring robust SI margins, jitter compliance, and eye quality.

• Transmitter Tuning: Perform detailed pre-emphasis and de-emphasis tuning to optimize transmitter settings and compensate for channel losses, maximizing link performance and eye opening.

• Advanced Lab Measurements: Operate high-end validation equipment including BERTs, real-time and sampling oscilloscopes (up to 50GHz+), TDR, and VNA to assess signal integrity and performance.

• PCB Signal Integrity Verification: Ensure PCB design compliance by validating return/insertion loss, crosstalk, impedance profiles, and via modeling against design simulations.

• Post-Silicon Characterization: Support early silicon bring-up and electrical validation, including performance testing across PVT corners, power/thermal correlation, and compliance metrics.

• Protocol Margining and BER Testing: Conduct PCIe and SerDes electrical open measurement (EOM) and bit error rate (BER) tests under stress conditions to validate system robustness.

• Cross-Functional Debug: Identify root causes of electrical failures, signal degradation, or timing violations, and work with design, layout, firmware, and systems teams to resolve issues.

• Documentation and Tracking: Log validation results, track open issues, and provide technical feedback and recommendations to internal stakeholders.

You may be a good fit if you have

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.

• Strong expertise in high-speed signal integrity validation, including SerDes, PCIe Gen5/6, and multi-gigabit interconnects.

• Experience with high-end lab tools: BERTs, >50GHz+ oscilloscopes, VNAs, TDR, etc.

• Deep understanding of transmission line theory, impedance control, jitter, and channel modeling.

• Strong lab skills, data analysis, and scripting (Python, MATLAB, etc.) for automation and reporting.

• Ability to work cross-functionally and communicate clearly in a fast-paced development environment.

Benefits

• Full medical, dental, and vision packages, with generous premium coverage

• Housing subsidy of $2,000/month for those living within walking distance of the office

• Daily lunch and dinner in our office

• Relocation support for those moving to West San Jose

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.