Head of Methodologies

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Job Summary

We’re looking for a Head of Methodologies to define and drive the design flows that power our cutting-edge silicon development. In this role, you’ll architect the entire methodology stack – owning everything from RTL design flows and verification infrastructure to physical implementation and signoff. You’ll be responsible for ensuring our EDA ecosystem, tools, and practices scale in lockstep with our ambitions. This is a rare opportunity to build foundational infrastructure and shape a cohesive, world-class methodology team at a company redefining what’s possible in AI hardware.

Key responsibilities

• Design and implement distributed methodologies to support scalable, high-performance development

• Build and lead a team of CAD engineers focused on automation, tooling, and continuous flow improvements

• Architect, deploy, and maintain robust RTL-to-GDSII flows supporting digital ASIC development across advanced nodes (4nm or below)

• Define and maintain RTL development flows, including lint, CDC, RDC, formal verification, and integration with simulation environments

• Develop methodologies to ensure high-quality handoff between RTL and physical design, including constraint management and timing intent preservation

• Partner with verification and DV teams to integrate regression automation, coverage collection, and results tracking into the frontend flow

• Collaborate with design teams to define and support Design for Test (DFT) methodologies, ensuring integration of scan, MBIST, and other test strategies into the overall flow

• Serve as the escalation point for EDA tool issues, coordinating with vendors to resolve bugs, deliver tool updates, and proactively qualify flows to ensure we are always leveraging the most up-to-date tools and capabilities as they evolve

• Develop and enforce best practices across synthesis, P&R, signoff, and physical verification flows

• Collaborate cross-functionally with silicon, verification, physical design, and software infrastructure teams to ensure frictionless tapeouts

• Build flows and practices explicitly aimed at shortening time to market

You may be a good fit if you have

• 10+ years of experience in CAD infrastructure, digital design methodology, or EDA tool development,

• A proven track record of designing and managing complex, distributed, and scalable EDA flows in production environments, including at least two successful tapeouts

• Familiarity with git workflows, including concepts such as git rebase

Strong candidates may also have experience with

• Scripting tools and automation frameworks (e.g., Python, Bazel, or tcl)

• Advanced knowledge of at least one major EDA tool suite (e.g., Synopsys or Cadence)

• Floorplanning, timing closure, and layout verification for high-performance digital designs

• Building CAD infrastructure for custom silicon teams at early-stage or high-growth hardware companies

Benefits

• Full medical, dental, and vision packages, with generous premium coverage

• Housing subsidy of $2,000/month for those living within walking distance of the office

• Daily lunch and dinner in our office

• Relocation support for those moving to San Jose (Santana Row)

Compensation Range

• $225,000 - $275,000

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed