Design Engineer, Google Cloud, Networking

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience architecting networking ASICs from specification to production or equivalent practical experience.
• Experience developing RTL for ASIC subsystems.
• Experience in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

• Master's degree or PhD in Computer Science or a related technical field.
• Experience with architecting networking switches, end points, and hardware offloads.
• Experience working with design networking like: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
• Experience with Mastery of TCP, IP, Ethernet, PCIE, and DRAM, and familiarity with Network on Chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
• Excellent problem solving and debugging skills.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Lead an ASIC subsystem and implement designs in SystemVerilog.
• Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
• Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
• Define efficient micro-architecture and block partitioning/interfaces and flows.
• Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.