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Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect

Folsom, CA, United States

USD 164K-358K Senior-level Full Time

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Found 2d ago
Tasks
Perks/Benefits
Skills/Tech-stack

Area Power Timing | C++ | Microarchitecture | Python | RTL | Synthesis | SystemVerilog | Verilog

Education

Master of Science | PhD

Roles

Design Engineer | Digital Design Engineer | Engineer | Memory Design Engineer

Regions

North America

Countries

United States

States

California, US

Cities

Folsom, California, US

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