Kolmogorov–Arnold Network (KAN) Hardware Accelerator for the Embedded Devices

Location: Lund, Sweden

Preferred starting date: Jan. 2025

Extent: 1-2 students, 30hp.

Thesis description

Recently, a new model called Kolmogorov-Arnold Networks (KAN) has been introduced. This model aims to replicate the capabilities of traditional deep neural networks (DNNs) but with significantly fewer parameters by utilizing parameterized B-spline functions with trainable coefficients. However, these B-spline functions pose unique challenges for hardware acceleration. This thesis focuses on hardware acceleration of KAN for embedded devices.

Objectives

Gain a deep understanding of the Kolmogorov-Arnold Networks, focusing on their structure, working principles, and the role of parameterized B-spline functions. Analyze the specific challenges posed by B-spline functions in the context of hardware acceleration, particularly for embedded devices. Develop and propose hardware architectures or modifications that can efficiently accelerate KANs on embedded platforms (RISCV, CIM, FPGA, etc.,). Implement the proposed hardware solutions and evaluate their performance in terms of area, power consumption, and latency compared to state of the art. Explore and apply optimization techniques to further enhance the performance of KANs on hardware.

Ziming Liu, Yixuan Wang, Sachin Vaidya, Fabian Ruehle, James Halverson, Marin Soljačić, Thomas Y. Hou, Max Tegmark, “KAN: Kolmogorov-Arnold Networks” 2024

Ziming Liu, Pingchuan Ma, Yixuan Wang, Wojciech Matusik, Max Tegmark, “KAN 2.0: Kolmogorov-Arnold Networks Meet Science” 2024

Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu “Hardware Acceleration of Kolmogorov–Arnold Network (KAN) for Lightweight Edge Inference”, ASP-DAC 2024.

Qualifications

Master student in Computer Science, Electrical Engineering or equivalent.

Theoretical background in areas such as computer architecture, embedded systems, machine learning, digital system design.

Understanding of CPU/GPU architecture, RISC-V, ISA design, in-memory compute, or dataflow architecture. Hands-on experience in Python, C/C++, ML libraries and RTL design.

Contact person

Johan Hokfelt (Johan.Hokfelt@huawei.com)