Member of Technical Staff (#91837)

Develop cycle-accurate and cycle-approximate simulator models for massively parallel computer systems and hardware accelerators. Understand the key characteristics of modern software algorithms and applications that can take advantage of such massive parallel machines - such as Data Analytics, Large Language Models used by Artificial Intelligence software, as well as Machine Learning algorithms. Perform pre-silicon and post-silicon verification of hardware designs that enable high performance execution of the modern workloads and applications mentioned. Architect/microarchitect specific units and subsystems of a Data Parallel Accelerator hardware capable of running hundreds of general-purpose programmable processor elements and hundreds of thousands of parallel computational threads on a single piece of silicon. 

Education:

• Master’s or foreign equivalent in Computer Engineering, Electrical Engineering, or related field 

Experience:

• 1 year of experience in job offered or related occupation.

Special Requirements:

• Must have at least 1 year of prior work experience in each of the following: 
• C/C++, System Verilog/ Verilog, Python. 
• Logic Design, RTL simulators, Data Structures and Algorithms.
• Computer Architecture, Assembly programming, Parallel Computing
• Deploying 3D object detection algorithms on DPU (Deep-learning Processor Unit) using Vitis-AI application flow. 
• Working on embedded speech recognition on FPGAs. 

•   **Telecommuting allowed for this position**

Worksite: 3315 Scott Blvd., Floor 4, Santa Clara, CA 95054 Contact: Jennifer Li, Chief of Staff