Standard Cell Design Engineer

Job Details:

Job Description: 

In this position, you will lead and participate in the design, development, validation, and delivery of standard cell libraries using leading process technologies for use in the design of Intel's next-generation SoCs and microprocessors. Responsibilities include, but are not limited to: - Design and implementation of the combinatorial, clock, power management, and sequential circuits for Intel's newest process technologies. - Parasitic extraction and circuit optimization for power/performance/robustness/density. - Library characterization for timing, noise, power, and variation models (non-linear delay models; composite current source models, parametric on-chip variation models). - Physical View (NDM, LEF, GDS, OASIS, OALIBS) generation for standard cell libraries. - Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. APL characterization and modeling. - Developing functional models behavioral Verilog, power udp Verilog and fault models. - Development of automation for library modeling, validation, quality checking, performance, and reliability verification. - The library build, validation, QA, release, and support. - Technically lead a team of engineers, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologies - Block Regression Activities - generation of PPA data and comparison to previous library revisions. Present to customers findings of Standard cell Block level data to ensure they are aware ahead of time. - Comparing PDK expectations to PPA observed at Standard cell level.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: You must possess a minimum of Master's degree in the field of electronics engineering. The successful candidate must possess excellent written and verbal communication skills, strong customer/result orientation and the ability to work with external and internal partners in a flexible manner. 2+ years' experience in the following: - Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics and FinFet characteristics. - Experience using industry-standard design automation tools in one or more of the areas: circuit simulation, std cell characterization, synthesis, place and route, physical design verification and reliability verification. - Experience in scripting (TCL, Perl, Python, ML) for design automation - Experience working in the Linux environment and its development tools Preferred Qualifications: 2+ Years experience in the following: - Specialization or experience in VLSI is preferred. - Experience in EDA tool/flow/methodology, product, and IP developments Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

          

Job Type:

College Grad

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Legal Disclaimer:

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