Senior Analog Layout Lead

Summary

Posted: Dec 12, 2024

Role Number:200582892

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, thoughtful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Join Apple's Silicon Engineering Group and be at the forefront of crafting the next generation of Apple's systems-on-chip (SOCs). Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Senior Analog Layout Leads to supply to the evolution of Analog/Mixed-Signal circuits, covering SerDes, PLLs, High Speed Parallel links and sensors. As a Senior Layout Lead, you'll play a role in translating design concepts into silicon, collaborating closely with circuit designers, and demonstrating sophisticated tools. Your work will involve creating custom analog designs to optimize the performance of Apple's extraordinary products. In this multifaceted and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams.

Description

Senior Layout Leads are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations.

Minimum Qualifications

• 10+ years of experience in analog/mixed-signal layout design, with a focus on deep submicron CMOS circuits and at least 3+ years in FinFet technologies
• Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python
• Familiar with Machine Learning and AI concepts
• Proven expertise in implementing analog layout designs, achieving tight matching, low noise, and low power consumption.
• Must recognize failure-prone circuit and layout structures, have experience with analog and DFM standard methodologies, and be able to identify the best approach to solving problems
• High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly
• Technical understanding of IR drop, RC delay, electro migration, self-heating, and coupling capacitance
• High proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.)
• Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager)
• Excellent communication skills and ability to work with multi-functional teams

Preferred Qualifications

• Cadence Innovus
• CAD Automation experience
• PCell creation experience