ASIC Design Engineer Intern (Summer 2025)

Canada- Ottawa- 383 Terry Fox- Bldg C

Ciena

Ciena is a global leader in optical and routing systems, services, and automation software.

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Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

The Opportunity: 

4 month work term: May – August 2025 

  

How You Will Contribute: 

 

Ciena Corporation is a global networking leader holding the #1 market position in our field.  The R&D headquarters in Ottawa is home to our world leading Digital Signal Processing (DSP) WaveLogic ASIC chipsets, forming the core of Ciena’s Optical Communications Systems.   

 

We are looking for a passionate and enthusiastic student to help develop and evolve the automation infrastructure used for our next generation ASIC devices.  As a member of the team, you will contribute to the infrastructure, design and integration of Ciena’s intellectual property into our next generation of ASICs. We are looking for students who have an interest in ASIC and Hardware Design with an interest in design, verification, and scripting. The position will be catered to a students’ previous experience, strengths, and expertise.  

 

You will enjoy working in a team environment, flexible working hours, and mentors who want to help you throughout the work term.    

 

In this role, you will.. 

  • Work with a fast-paced team developing large scale DSP ASICs for optical communications. There are two key jobs we are hiring for. Students will be trained and will have access to key engineers while working on these projects. Some projects can be extended to 8 months. 

Develop and deploy a tool for Cell and Process exploration

  • Understand the ASIC Standard Cell flow 

  • Work with the Integration Team Engineer to extract key transistor and cell metrics 

  • Using simulation tools, exercise the cells to extract key timing details and 

  • Assembling the data into a spreadsheet, create a dynamic spreadsheet that can show how varying the voltage/process/temperature affects the key parameters which govern the ASIC. 

Develop Key Metrics extraction Tool 

  • Understand the ASIC Standard cell flow 

  • Using advanced search and analytical techniques, extract key metrics from ASIC characterization data 

  • Present the data in a suitable tabular and graphical format. 

  • Work with Key engineers to understand the flow and how it impacts the key metrics when choosing an ASIC fow. 

You will gain… 

  • Experience building complex scripts and applications using Excel, Python, TCL 

  • A deeper understanding of ASIC and Hardware techniques  

  • First-hand exposure to real world class ASIC developments using the latest ASIC technologies  

  • A strong sense of responsibility for quality and completion of assigned tasks 

The Must Haves: 

  • Programming experience (ideally using at least one of Java, Python, or System Verilog)  

  • Familiarity with Linux based development environments  

Assets: 

  • Previous experience ASIC or FPGA development programs  

  • Experience using Jenkins  

  • Experience contributing to open-source projects  

  • Strong analytical and debugging skills  

  • Familiarity with Agile JIRA, Confluence, GIT  

  • Interest in applying Machine Learning and AI techniques  

The pay range for this position is $24.50-$33.00/hour

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.


In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.  Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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Job stats:  3  2  0
Category: Engineering Jobs

Tags: Agile ASIC Design Confluence Excel FPGA Git Java Jenkins Jira Linux Machine Learning Open Source Python R R&D

Perks/benefits: Career development Competitive pay Flex hours Flex vacation

Region: North America
Country: Canada

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