ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Tasks
- Analyze microarchitectures and architectures
- Collaborate with verification and backend teams
- Create microarchitectures
- Develop RTL designs
- Execute Lint checks
- Execute clock domain crossing checks
- Implement SystemVerilog RTL
- Perform synthesis and timing closure
Perks/Benefits
- 401k matching
- Dental insurance
- Employee assistance program
- Flexible spending accounts
- Health insurance
- Mental health support
- Paid time off
- Parental leave
- Vision insurance
Skills/Tech-stack
ARM | ASIC design | Clock Domain | Clock Domain Crossing | DSP | Digital Signal | Digital Signal Processing | Domain crossing | Formal verification | Lint | Machine Learning | Machine Learning Inference | Microarchitecture | Perl | Python | RTL constraints | Register Transfer | Register Transfer Level | Signal Processing | Synthesis | SystemVerilog | Timing Analysis
Education
Roles
Regions
Countries
States
Cities
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