ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Tasks
- Analyze microarchitectures and architectures
- Collaborate with verification and back-end teams
- Create design constraints
- Create microarchitectures
- Deliver synthesis and timing clean designs
- Develop RTL designs
- Execute Lint checks
- Execute clock domain crossing checks
- Implement SystemVerilog RTL
Perks/Benefits
Skills/Tech-stack
ARM | ASIC design | Clock Domain | Clock Domain Crossing | DSP | Domain crossing | Formal verification | Linting | Microarchitecture | Microarchitecture analysis | Perl | Python | RTL | Synthesis | SystemVerilog | Timing closure
Education
Roles
Regions
Countries
States
Cities
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