ASIC Design Engineer II, Cloud-Scale Machine Learning Acceleration team
Tasks
- Analyze design microarchitecture or architecture trade offs
- Collaborate with architects designers verification and back end teams
- Debug RTL test failures
- Deliver synthesis and timing clean design with constraints
- Develop microarchitecture and implement SystemVerilog RTL
- Implement RTL for high performance area and power efficiency
- Integrate subsystems into top-level SOC
- Perform lint checks and clock domain crossing checks
Perks/Benefits
Skills/Tech-stack
Assertions | Clock Domain Crossing | Domain crossing | Linting | Python | RTL design | Synthesis | SystemVerilog | Timing Analysis
Education
Roles
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