Power lead - High performance cores and AI/ML IPs
Santa Clara, CA, United States
USD 209K-266K (estimate) Senior-level Full Time
Tasks
- Analyze energy using existing workflows
- Define low power architecture
- Determine power reduction functionality with logic teams
- Develop IP power models
- Develop core IP power budget
- Drive micro-architecture design
- Establish energy tracking workflows
- Implement RTL energy optimizations
- Improve power modeling with cross functional teams
- Maintain chip power dashboard
- Perform power simulation and modeling
- Run workloads for power analysis
- Select workloads for power estimation
Perks/Benefits
Skills/Tech-stack
ASIC | Accelerator design | Energy tracking | Low power | Low power architecture | Microarchitecture | Out-of-order | Perl | Power Estimation | Power Modeling | Power Optimization | Power architecture | Power budgeting | Power emulation | Power intent | Power simulation | Python | RTL | TCL
Education
N/A
Roles
Regions
Countries
States
Cities
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