Quantum Cryo CMOS Design Enablement
USA - New York - Malta, United States
USD 143K-247K Senior-level Full Time
Tasks
- Build cryogenic test lab capabilities
- Communicate progress risks and mitigation
- Correlate model to silicon data
- Define cryogenic CMOS design enablement roadmap
- Define technical milestones and deliverables
- Deploy design flows and simulation methodologies
- Design test structures
- Develop compact models
- Develop cryogenic CMOS PDKs
- Develop variability models
- Drive cross-functional execution
- Establish electrical characterization methodologies
- Execute model and PDK continuous improvement
- Oversee test chip design
- Partner with EDA vendors
- Perform parameter extraction
- Validate device models
Perks/Benefits
- N/A
Skills/Tech-stack
Chip Design | Compact model development | Correlation | Cryogenic electronics | Design Flows | Device modeling | EDA Engagement | Electrical characterization | Model Development | Parameter extraction | Simulation methodologies | Statistical modeling | Test Chip | Test Chip Design | Test infrastructure | Variability modeling
Education
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