Quantum Cryo CMOS Design Enablement
USA - New York - Malta, United States
USD 98K-176K Mid-level Full Time
Tasks
- Analyze characterization data trends variability and impact
- Collaborate with EDA vendors on modeling tools
- Correlate silicon data with simulations
- Create compact models
- Design and evaluate test chips
- Design test structures
- Develop cryogenic CMOS PDKs
- Develop design flows for PDK deliverables
- Develop test sites
- Document methodologies, assumptions, and results
- Execute electrical characterization plans
- Extract model parameters
- Implement model integration in EDA environments
- Integrate models into EDA tooling
- Validate models across temperature regimes
Perks/Benefits
- N/A
Skills/Tech-stack
Chip Design | Compact Models | Cryogenic CMOS | Data Analysis | Design Kit | Device modeling | EDA Integration | EDA Tooling | Electrical characterization | Electrical simulation | Model Validation | Parameter extraction | Process Design | Process design kit | Semiconductor Device | Semiconductor device modeling | Site development | Statistical Data Analysis | Statistical data | Structure design | Temperature Scaling | Test Chip | Test Chip Design | Test Site Development | Test structure | Test structure design | Variability modeling
Education
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