Quantum TSV Integration Engineer
USA - New York - Malta, United States
USD 98K-176K Senior-level Full Time
Tasks
- Co optimize TSVs with the full packaging stack
- Coordinate with equipment vendors for new tooling qualification and materials
- Create TSV integration flows specifications and design rules
- Define TSV architecture and geometries
- Define TSV process tool requirements for DRIE deposition wafer thinning and reveal
- Develop next generation TSV scaling strategies and via concept evaluations
- Develop superconducting interposer and 3D integration TSV solutions
- Improve TSV yield process robustness and integration reliability under cryogenic conditions
- Integrate TSVs with bump interconnect and RDL layers
- Lead TSV process development for cryogenic and superconducting applications
- Optimize TSV designs for low loss signal transport and cryogenic stability
- Optimize interface integrity between liner dielectric and substrate
- Own TSV integration flows across etch deposition dielectric metallization and wafer processing
- Perform failure mode analysis and root cause corrective actions
- Plan process integration for prototyping and qualification
- Select compatible TSV liner and dielectric materials for cryogenic superconducting operation
- Support cryogenic electrical characterization and signal integrity testing
- Support thermal leakage characterization across vias
Perks/Benefits
- N/A
Skills/Tech-stack
2 5D | 2 5D packaging | 3D packaging | ALD | CVD | Cause analysis | Cryogenic engineering | DRIE | Deep Silicon Etching | Design Rules | Failure analysis | Film deposition | Materials Selection | Microbump Technology | Microwave engineering | PVD | Packaging Integration | Process Integration | Project Planning | RF Engineering | Root Cause Analysis | Root cause | Signal Integrity | Silicon Etching | Superconductivity | Thermal analysis | Thin film | Thin film deposition | Via Etch | Wafer processing
Education
Roles
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