R&D Engineer, Sr Engineer (C/C++, Data structures, Algorithm, FPGA)
Tasks
- Apply Verilog and VHDL at RTL level
- Automate testing strategies
- Collaborate with PV teams on testing
- Conduct code reviews and design discussions
- Design and develop EDA software systems
- Implement and optimize data structures and algorithms
- Perform digital logic design optimization
- Prepare designs for partitioning and estimate design metrics
- Support hardware software co-design workflows
- Troubleshoot and debug software systems
Perks/Benefits
Skills/Tech-stack
Algorithm Optimization | C# | C++ | Data Structures | Digital Logic | Digital Logic Design | FPGA | Graph Algorithms | Logic Design | RTL | Software Optimization | VHDL | Verilog
Education
Roles
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