RTL Design Engineer, Machine Learning Accelerators
Tasks
- Design and document ASIC blocks
- Propose and develop chip design improvements
- Verify functionality and timing
- Work with software teams on interfaces and documentation
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC design | Code review | Machine Learning | Machine Learning Accelerators | Memory hierarchy | Processor design | RTL design | Refactoring | SystemVerilog | Testing | Verilog
Education
Roles
Regions
Countries
States
Cities
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