RTL Design Engineer, Multimedia and Machine Learning Accelerators
Tasks
- Analyze coverage
- Automate tasks with scripts
- Create test plans
- Debug simulation issues
- Develop RTL for power performance area
- Participate in synthesis
- Perform RTL coding
- Perform RTL verification
- Run UPF checks
- Run formal verification
- Run lint and CDC checks
- Support FPGA/silicon bring-up
- Support power closure
- Support timing closure
- Track progress
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC | C plus plus | C# | Clock Domain Crossing | Coverage analysis | Domain crossing | FPGA | Field Programmable Gate Array | Formal verification | Lint | Perl | Power Format | Power analysis | Python | RTL design | Register Transfer Level | Synthesis | SystemVerilog | Test Planning | TestBench | Timing Analysis | Unified power format | Verilog
Education
Bachelor of Engineering | Bachelor of Science | Master of Science | PhD
Roles
Regions
Countries
States
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