(Senior) Researcher - Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design

Tasks

• Architect networks on chip interconnects
• Co-design computation and communication for wafer scale systems
• Design flow control and protocols
• Explore network topology and routing algorithms
• Map LLM training and inference workloads to wafer scale systems
• Optimize LLM parallel execution and workload decomposition
• Publish research in top-tier conferences and journals
• Schedule and place tasks to improve performance and energy efficiency

Perks/Benefits

• Professional development
• State of the art tools

Skills/Tech-stack

Computer Architecture | Energy Efficiency | Flow Control | High Performance | High-Performance Computing | Interconnection networks | LLM Parallelism | Networks on chip | Performance Computing | Performance Modeling | Routing Algorithms | Task Scheduling | Topology Exploration | Workload mapping