Silicon Engineer, Digital Research, Quantum AI
Goleta, CA, USA; Mountain View, CA, USA
USD 163K-237K Mid-level Full Time
Tasks
- Automate design flows
- Conduct design reviews
- Create technical specifications
- Develop RTL
- Develop architectural requirements
- Develop cryogenic digital design models
- Develop documentation
- Develop test infrastructure
- Develop test plans
- Implement digital systems
- Perform physical design
- Support silicon bring-up
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC development | Analog design | Cadence Genus | Cadence Innovus | Cell Modeling | Custom Library Development | Design Compiler | Design automation | Device physics | Field Programmable Gate Array | IP integration | Library Development | Logic synthesis | Physical Design | Physical synthesis | Python | RTL to Physical Design | Register Transfer | Register Transfer Level | Rust | Standard cell | Standard cell modeling | Synopsys Design Compiler | Synopsys Primetime | SystemVerilog | Third Party | Third-party IP | Third-party IP integration | Timing closure | Verilog
Education
Regions
Countries
States
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