Staff ASIC Design Engineer – AI/ML Hardware IP
Tasks
- Collaborate on test plans debug and coverage analysis
- Conduct lint CDC and synthesis flow analysis
- Create SVA assertions
- Define micro-architecture and specifications
- Develop performance optimized RTL design
- Integrate sub-IP blocks into SoC
Perks/Benefits
Skills/Tech-stack
CDC | Clock Domain | Clock Domain Crossing | Design Compiler | Design for Power | Domain crossing | Formality | Lint | Logic synthesis | Perl | Power intent | PrimeTime | Python | Questa | RTL design | SVA | Spyglass | Synthesis timing | SystemVerilog | TCL | UPF | VCS | Verdi | Verilog | Xcelium
Education
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