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RTL Design Engineer, Multimedia and Machine Learning Accelerators

Mountain View, CA, USA

USD 163K-237K Senior-level Full Time

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Found 4h ago
Tasks
Perks/Benefits
Skills/Tech-stack

ASIC | C plus plus | C# | Clock Domain Crossing | Coverage analysis | Domain crossing | FPGA | Field Programmable Gate Array | Formal verification | Lint | Perl | Power Format | Power analysis | Python | RTL design | Register Transfer Level | Synthesis | SystemVerilog | Test Planning | TestBench | Timing Analysis | Unified power format | Verilog

Education

Bachelor of Engineering | Bachelor of Science | Master of Science | PhD

Roles

Design Engineer | Engineer | RTL Design Engineer

Regions

North America

Countries

United States

States

California, US

Cities

Mountain View, California, US

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