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4 results
for Design Verification Engineer
(Role)
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ASIC | C plus plus | C# | EDA Tools | EmulationSenior-level Full TimeSunnyvale, CA10d ago
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ACE | APB | ARM | AXI | Constrained randomSenior-level Full TimeMountain View, CA, USA12d ago
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Staff Design Verification Engineer (AI/ML) USD 127K-175KAI/ML | Back Annotation | Behavioral Abstraction | Cadence JasperGold | Cadence XceliumSenior-level Full TimeUS, AZ, Chandler, East Elliot, United …12d ago
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Silicon Design Verification Engineer, Quantum AI USD 138K-198KARM | C-based testing | Chip verification | Constrained random | Constrained random verificationMid-level Full TimeMountain View, CA, USA; Goleta, CA, …1mo ago