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for System Verilog
(Skill/Tech stack)
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Mid-level Full TimeSundbyberg, Sweden18d ago
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MLA IP Design Verification Engineer, Annapurna Labs USD 136K-212KDesign Validation | Design validation methods | Hardware validation | Hardware verification | Plan developmentCareer growth opportunities | Inclusive team culture | Mentorship | Work-life balanceMid-level Full TimeAustin, Texas, USA1mo ago