RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead
Tasks
- Collaborate with product definition and architecture teams
- Coordinate with power and synthesis teams
- Create design collateral including timing constraints and UPF
- Define block-level design
- Develop assertions for white box testing
- Develop microarchitecture strategies
- Drive Lint CDC FV UPF checks
- Lead RTL coding
- Perform function and performance simulation debug
Perks/Benefits
- N/A
Skills/Tech-stack
Assertions | Clock Domain | Clock Domain Crossing | Computer Architecture | Domain crossing | Formal verification | Logic Design | Low power | Low power microarchitecture | NOC design | RTL design | Synthesis | SystemVerilog | UPF | Verilog
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