Sr Principal Engineer AI/ML
USA - California - Santa Clara, United States
USD 171K-325K Senior-level Full Time
Tasks
- Assist RTL verification
- Configure design features for power performance area timing
- Define RTL development
- Design AI enabled matrix engine
- Design RISC-V vector CPU core
- Design critical CPU blocks
- Design custom RISC-V vector extensions
- Drive microarchitecture development
- Partner on physical design validation
- Support functional verification strategy
Perks/Benefits
- N/A
Skills/Tech-stack
ARM | Branch prediction | CPU microarchitecture | Cache Coherency | Cache and memory subsystems | Data Path | Functional verification | Hardware multithreading | In order execution | Instruction Decode | Instruction fetch | Instruction scheduling | Load store execution | Load/store | Logic Design | MIPS | Memory consistency | Memory subsystems | Order execution | Out-of-order | Out-of-order execution | Perl | Power Optimization | Python | RISC-V | RTL | Register Renaming | Reorder Buffer | SIMD | Simulation | SoC integration | Store Execution | System Verilog | Timing Analysis | VHDL | Vector data | Vector data path | Verilog | Virtualization | Waveform debugging
Education
Regions
Countries
States
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