Senior Power Analysis and Optimization Engineer
US, CA, Santa Clara, United States
USD 136K-264K Senior-level Full Time
Tasks
- Analyze full chip and unit level power
- Automate power analysis pipelines
- Build and deploy machine learning reinforcement learning models
- Conduct design space exploration
- Develop power aware models and flows
- Interpret power data and propose root causes
- Optimize dynamic power management
- Perform anomaly detection
- Prototype architectural features in Verilog
- Recommend architectural and micro architectural optimizations
- Run comparative power analysis across workloads
- Train large language models for power analysis
- Tune power efficient configurations and policies
Perks/Benefits
Skills/Tech-stack
ASIC design | Anomaly Detection | C++ | Data analytics | Dynamic Power | Dynamic Power Management | Gate Level Power | Gate-level | Language Models | Large Language Models | Low power | Low power design | Machine Learning | Perl | Power Estimation | Power Management | Power design | PowerArtist | PrimePower | Python | RTL | RTL Architect | Reinforcement Learning | Verilog
Education
N/A
Regions
Countries
States
Cities
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