RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead
Tasks
- Collaborate on timing constraints and UPF collateral
- Define block level design interfaces and clocking
- Develop assertions for white box testing
- Develop microarchitecture and coding strategies
- Drive Lint CDC FV UPF checks
- Lead RTL coding and SOC integration debugging
- Perform function and performance simulation debug
- Work with power synthesis and DFT teams
Perks/Benefits
- N/A
Skills/Tech-stack
Assertions | Box testing | CDC | Clocking | Formal verification | Lint | Logic Design | Low power | Microarchitecture | NOC design | Pipeline | Power Aware Synthesis | RTL | Simulation debugging | SystemVerilog | Timing closure | Transaction flow | UPF | Verilog | Waveform debugging | White-box | White-box testing
Education
Bachelor of Engineering | Bachelor of Science | Master of Engineering | Master of Science | PhD
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