ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Tasks
- Analyze designs for trade offs
- Collaborate with cross-functional teams
- Create microarchitectures
- Deliver synthesis and timing clean designs
- Develop RTL designs
- Implement SystemVerilog RTL
- Run lint and clock domain crossing checks
- Support pre-silicon and post-silicon validation
Perks/Benefits
Skills/Tech-stack
4G | 5G-NR | 80211ad | ARM | Cellular | Clock Domain | Clock Domain Crossing | DSP | Domain crossing | Formal verification | Linting | Microarchitecture | Microwave backhaul | Perl | Python | RF standards | RTL | SoC verification | Synthesis | System on chip | SystemVerilog | Timing Analysis | WiMax
Education
Roles
Regions
Countries
States
Cities
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