AI/ML ASIC Architect
USD 163K-235K (estimate) Senior-level Full Time
Tasks
- Analyze LLM workloads and characterize ASIC and datacenter solutions for performance improvements
- Architect memory efficient inference and training systems
- Author AI ML accelerator ASIC architecture specifications
- Define I/O subsystem and PCIe DMA architectures
- Define hardware software firmware interactions for SoC subsystems and host CPUs
- Design modular I O subsystem architectures for chiplet monolithic or 3D
- Develop AI storage solutions based system architecture
- Guide pre silicon design verification and post silicon validation
- Perform hardware software co-optimization for performance power area and endurance
- Scope SoC requirements and define architectural requirements
Perks/Benefits
- N/A
Skills/Tech-stack
ARM | ASIC architecture | AXI interconnect | Area Optimization | Attention Mechanisms | Bandwidth Optimization | CUDA | CXL | Cache optimization | Continuous batching | DMA | Emulation | Endurance Optimization | Firmware | Flash Attention | GPU Architecture | HBM | HBM Bandwidth | HBM bandwidth optimization | I/O | I/O subsystem | KV cache | KV cache optimization | Memory controller | Microarchitecture | Mixture of Experts | Model Parallelism | NAND flash | NOC | NVM subsystem | Network on Chip | PCIe | Performance Engineering | Power Optimization | Pruning | Quantization | RTL | Simulation | SoC Architecture | Speculative decoding | TPU architecture | Transformer Architectures | UCIe | XPU architecture
Education
Roles
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