Senior Power Analysis and Optimization Engineer, AI-LLM Systems
US, CA, Santa Clara, United States
USD 136K-264K Senior-level Full Time
Tasks
- Analyze full chip power
- Analyze unit level power
- Automate power analysis pipelines
- Build data driven power optimization models
- Deploy power optimization policies
- Detect power anomalies
- Develop power-aware models
- Explore design space for power
- Optimize dynamic power management
- Partner with cross-functional engineering teams
- Perform comparative power analysis
- Productionize power analysis flows
- Propose candidate power fixes
- Prototype power architectural features in Verilog
- Recommend architectural optimizations
- Recommend power efficient configurations
- Recommend root causes
- Train LLMs for power analysis
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC design | Anomaly Detection | C plus plus | Data analytics | Design Space Exploration | Dynamic Power Management | Gate Level Power Analysis | Gate-level | Language Models | Large Language Models | Low power | Low power design | Machine Learning | Perl | Physical Design | Power Artist | Power Management | Power analysis | Power design | PrimePower | Python | RTL | RTL Architect | Reinforcement Learning | Space exploration | Verilog
Education
Regions
Countries
States
Cities
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