Staff Engineer AI/ML
USA - California - Santa Clara, United States
USD 106K-205K Senior-level Full Time
Tasks
- Assist RTL verification for performance goals
- Collaborate to implement and validate physical design aspects
- Configure RTL design features for power performance area and timing
- Define RISC V vector CPU core and custom extensions
- Design AI enabled matrix engine
- Develop microarchitecture and specifications
- Drive microarchitecture design for CPU core blocks
- Perform CPU performance power and area strategy exploration
- Support functional verification and verification strategy
Perks/Benefits
- N/A
Skills/Tech-stack
Branch prediction | CPU microarchitecture | Cache | Cache Coherency | Functional verification | In order execution | Instruction scheduling | Load store execution | Load/store | Memory consistency | Order execution | Out-of-order | Out-of-order execution | Perl | Python | RISC-V | RTL | Register Renaming | Reorder Buffer | Store Execution | System Verilog | VHDL | Verilog | Waveform debugging
Education
Regions
Countries
States
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