ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
Tasks
- Analyze microarchitectures for tradeoffs
- Collaborate with cross-functional hardware teams
- Develop RTL designs
- Execute clock domain crossing checks
- Implement SystemVerilog RTL
- Perform synthesis and timing closure
- Run lint checks
Perks/Benefits
Skills/Tech-stack
ASIC design | Area Optimization | Clock Domain | Clock Domain Crossing | Domain crossing | Linting | Microarchitecture | Performance optimization | Power Optimization | RTL | Synthesis | SystemVerilog | Timing closure
Education
Roles
Regions
Countries
States
Cities
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