Staff ASIC Design Engineer – AI/ML Hardware IP
Toronto, Ontario; Toronto, Ontario
A CAD 135K-187K (estimate) Senior-level Full Time
Tasks
- Collaborate on test plans debug and coverage analysis
- Create SVA assertions for formal verification
- Define micro architecture specs
- Develop performance optimized RTL
- Integrate sub-IP blocks into SoC
- Run lint CDC and synthesis analysis
Perks/Benefits
Skills/Tech-stack
ASIC design | C# | CDC analysis | Clock Domain | Clock Domain Crossing | Design Compiler | Domain crossing | Formal verification | Formality | Linting | Logic synthesis | Perl | Power intent | PowerPro | PrimeTime | Python | Questa | RTL design | SVA | Spyglass | SystemVerilog | TCL | UPF | UPF CLP | VCS | Verdi | Verilog | Xcelium
Education
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