Staff Digital Design Engineer (AI/ML)
US, AZ, Chandler, East Elliot, United States
USD 131K-190K (estimate) Senior-level Full Time
Tasks
- Apply AI ML to improve synthesis results and optimization
- Collaborate with analog teams to integrate digital analog interfaces
- Conduct architecture and design reviews
- Develop digital subsystems for mixed-signal ICs
- Execute RTL design and optimization in Verilog SystemVerilog
- Implement DFT scan insertion ATPG BIST and fault coverage closure
- Perform static timing analysis and power analysis
- Run logical equivalence checking
- Run synthesis with timing and placement constraints
- Validate and support tape out silicon bring up and production release
Perks/Benefits
- N/A
Skills/Tech-stack
Education
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