Principal Engineer, Design Technology Co-optimization
USD 220K-311K Senior-level Full Time
Tasks
- Collaborate with foundry technology teams and EDA partners
- Drive optimization of standard cell libraries
- Interface with foundry customers to identify technology gaps
- Optimize library circuits with physical design engineers
- Optimize standard cell library content for product level power performance and area
- Tune cell layout for improved performance power and area
Perks/Benefits
Skills/Tech-stack
Area analysis | Circuit characterization | Design technology | Design technology co-optimization | Electrical characteristics | Foundry EDA IP ecosystem | Layout Engineering | Layout effects | Library design | Local layout effects | MOSFET electrical characteristics | Power performance area | Power-performance-area analysis | Power/performance | Pre and post Si benchmarking | SPICE simulation | Semiconductor design | Semiconductor design technology co optimization | Signoff methodology | Standard Cell Library | Standard cell | Standard cell library design
Education
Roles
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