RTL Design Engineer, Machine Learning
Tasks
- Collaborate with software teams on interfaces
- Define block functionality and timing
- Design and document ASIC blocks
- Develop documentation for ASIC interfaces
- Propose and develop ASIC design improvements
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC | Code review | High Performance | High-Performance Design | Low power | Low power design | Memory hierarchy | Performance design | Power design | Processor design | RTL design | Refactoring | Register Transfer | Register Transfer Level | Scripting | SoC | SystemVerilog | Testing | Verilog
Education
Regions
Countries
States
Cities
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