Master Thesis Student – Compiler Optimization for RISC-V Processors
BEL - Flemish Brabant - Leuven - Haasrode, Belgium
EUR 49K-60K (estimate) None Part Time
Tasks
- Analyze RISC-V microarchitecture
- Analyze performance bottlenecks
- Benchmark performance
- Collaborate on hardware-software co-optimization
- Design LLVM compiler optimizations
- Document thesis findings
- Identify instruction fusion opportunities
- Identify instruction scheduling opportunities
- Implement LLVM compiler enhancements
- Optimize compiler code generation
- Profile performance
- Study processor pipelines
- Validate compiler optimizations
Perks/Benefits
Skills/Tech-stack
Benchmarking | C# | C++ | Code generation | Compiler optimization | Computer Architecture | Instruction Fusion | Instruction scheduling | LLVM | Linux | Profiling | RISC-V
Education
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