Senior Integration & Yield Engineer — Superconducting Quantum Circuits H/F
Tasks
- Build automated yield dashboards
- Coordinate device failure investigation at room and cryogenic temperatures
- Define integration flows of process of reference
- Develop python tools for design to wafer pipeline
- Develop strategies to reduce inductance and frequency non uniformity
- Establish design for manufacturability guidelines
- Generate wafer layouts from device designs
- Implement design rule manual extensions
- Lead corrective and preventive actions using structured problem solving
- Maintain lookup tables linking design parameters to fabrication
- Maintain reference fabrication flows and process KPIs
- Own yield monitoring across fabrication flows
- Perform root cause analysis for yield detractors
- Run statistical process analysis for process stability
Perks/Benefits
- French language courses covered by company
- Health coverage
- Kitchen access
- Meal vouchers
- Mental health support
- Parental plan
- Remote work policy
- Subsidized sports membership
- Transportation coverage
- Vacation plus RTT
Skills/Tech-stack
5 Whys | Atomic force microscopy | Cause analysis | Circuit fabrication | Cryogenic testing | DOE | Data Analysis | Design Rule Manual | Design for manufacturability | Design rule | Electrical testing | Electron microscopy | FMEA | Inline metrology | Ishikawa | JMP | Python | Root Cause Analysis | Root cause | SPC | Scanning electron microscopy | Semiconductor nanofabrication | Statistical Analysis | Superconducting Circuit Fabrication | Wafer Layout
Education
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