Senior Staff ASIC Design Egineer - AI/ML Hardware IP
Tasks
- Analyze design flows
- Create functional coverage
- Debug RTL issues
- Define micro-architecture
- Develop RTL
- Develop test plans with verification
- Execute linting CDC synthesis power intent
- Integrate sub-IP blocks
- Lead cross functional design integration
- Optimize performance area power
- Support formal and white box verification
- Write SVA assertions
Perks/Benefits
- N/A
Skills/Tech-stack
0in | AHB | AI/ML | AI/ML hardware | AI/ML hardware acceleration | ASIC design | AXI | C# | CDC | CLP | Clock/reset | Clock/reset architecture | DCG NXT | FIFO | Formal verification | Formality | Hardware acceleration | ML Hardware Acceleration | Memory controller | Perl | Power-aware design | PowerPro | PrimeTime | Python | Questa | RTL design | Reset architecture | Simulation | Spyglass | Static Timing | Static Timing Analysis | Synthesis | SystemVerilog | TCL | Timing Analysis | UPF | VCS | Verdi | Verilog | Xcelium
Education
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