Find jobs in AI/ML, Data Science and Big Data
15 results
for Static Timing
(Skill/Tech stack)
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ASIC physical design | C++ | C++14 | Distributed Computing | High PerformanceEntry-level Full TimeChina, Shanghai1d ago
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Algorithms | C++ | CI/CD | Convolutional Neural Networks | Data Structures401k | Dental insurance | Health insurance | Paid leave | Vision insuranceMid-level Full TimeSan Diego (Treena St), United States5d ago
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Algorithms | C++ | CDC | CI | CI/CD401k | Dental insurance | Equity | Health insurance | Incentive compensationSenior-level Full TimeSan Diego (Treena St), United States5d ago
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AI/ML driven ASIC Design and Implementation Automation Engineer INR 1500K-4000KAlgorithms | Bitbucket | C++ | CI/CD | Clock DomainMid-level Full TimeBangalore, India7d ago
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AI/ML driven ASIC Design and Implementation Lead Engineer INR 2500K-5500KAlgorithms | Bitbucket | C++ | CDC | CI/CDSenior-level Full TimeBangalore, India7d ago
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Algorithms | Bitbucket | C++ | CDC | CI/CD401k | Dental insurance | Health insurance | Paid leave | Vision insuranceMid-level Full TimeSan Diego (Treena St), United States7d ago
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AI/ML driven ASIC Design and Implementation Automation Engineer INR 1500K-4000KC++ | CDC | CI/CD | Clocking | DFTMid-level Full TimeBangalore, India7d ago
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AI/ML driven ASIC Design and Implementation Automation Engineer INR 1500K-4000KAlgorithms | Bitbucket | C++ | CDC | CI/CDMid-level Full TimeBangalore, India7d ago
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Senior SoC Power Analysis & Optimization Engineer USD 120K-600KAI workload | AI workload characterization | ASIC | Clock gating | Gate Level Analysis401k match | Company holidays | Flexible spending accounts | Health, dental, vision, and life insurance | Home tech setup reimbursementSenior-level Full TimeMountain View, CA R12d ago
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AI/ML Logic Design Engineer-Senior USD 127K-190KDigital design | EDA Tool | EDA tool debugging | Git | Instruction setSenior-level Full TimeAustin, Texas, United States of America20d ago
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Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization USD 266K-392KC plus plus | Clock Domain | Clock Domain Crossing | Clock analysis | Constraint managementSenior-level Full TimeSan Jose, California, United States, United …26d ago
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Design Technology Co-Optimization Engineer USD 138K-198KCMOS device physics | Datacenter IP blocks | Design Rule Manual | Design rule | Device physicsMid-level Full TimeSunnyvale, CA, USA1mo ago
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Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning USD 136K-212KASIC physical design | ECO flow | EDA Tools | Perl | Physical DesignMid-level Full TimeCupertino, California, USA1mo ago
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Software R&D Engineer, RTL Optimization Tools USD 136K-218KAdversarial Networks | C++ | Clock distribution | Clocking | Design for testabilitySenior-level Full TimeUS, CA, Santa Clara, United States1mo ago
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ASIC implementation | Circuit analysis | EDA Tools | EMIR | Grid design401k matching | EAP | Flexible spending accounts | Health insurance | Medical Advice LineSenior-level Full TimeCupertino, California, USA1mo ago