Sr. SDE, MLA hardware/software co-design, Annapurna Labs Machine Learning Acceleration
Tasks
- Build and test next generation AI chips
- Develop and maintain automation frameworks for post silicon flow
- Drive pre-silicon hardware/software co-development
- Perform ASIC implementation synthesis STA and physical design
- Verify SoC end to end functionality and performance
- Write bare metal software and ML workloads
Perks/Benefits
- 401k matching
- Career growth
- Dental insurance
- Health insurance
- Mentorship
- Paid time off
- Parental leave
- Vision insurance
Skills/Tech-stack
ASIC | Agile | BDD | Bare Metal | Bring-up | C# | CDMA | CI | CI/CD | Deep Submicron | Embedded C | Emulation | Git | I2C | I3C | L2 Algorithms | Linker scripts | Low power | Low power design | MAC layer | MATLAB | MIMO | Modem L1 Algorithms | Modem L2 Algorithms | Multiple Power Islands | NVIC) | OFDM | OFDMA | PHY MAC Layer | PHY/MAC | Page tables | Physical Design | Physical Synthesis Methodology | Physical synthesis | Post Silicon Validation | Post-silicon | Power design | Power gating | Python | RF Engineering | SOC bring-up | SPI | STA | Scripting | Silicon validation | Synthesis | SystemC | TDD | TDMA | Test Setup | Test setup automation | UART | UVM | Verification | Wireless Communications
Education
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