Find jobs in AI/ML, Data Science and Big Data
9 results
for UVM
(Skill/Tech stack)
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Applied AI Engineer, Silicon Engineering USD 150K-275KC++ | CI/CD | Context engineering | Continuous integration | Coverage analysisDaily meals | Housing subsidy | Medical, dental & vision coverage | Relocation support | Unlimited compute budgetMid-level Full TimeSan Jose1d ago
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ASIC | C plus plus | C# | EDA Tools | EmulationSenior-level Full TimeSunnyvale, CA10d ago
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ACE | APB | ARM | AXI | Constrained randomSenior-level Full TimeMountain View, CA, USA12d ago
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Staff Design Verification Engineer (AI/ML) USD 127K-175KAI/ML | Back Annotation | Behavioral Abstraction | Cadence JasperGold | Cadence XceliumSenior-level Full TimeUS, AZ, Chandler, East Elliot, United …12d ago
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Generative AI Expert for Verification Automation EUR 54K-70KAI guardrails | Code Coverage | Correctness | Coverage Driven Verification | DeterminismSenior-level Full TimeAgrate Brianza, Italy17d ago
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Forward Deployed AI Engineer USD 180K-325KAgentic patterns | Distributed Systems | EDA | Fine Tuning | Machine LearningMid-level Full TimeNew York City25d ago
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Embedded Design Engineer - FPGA Academy GBP 34K-34KC++ | Design verification | Embedded C | FPGA | IntegrationAccess to online courses | Bonus scheme | Dental coverage | Employee networks | Financial adviceMid-level Full TimeGB - Newcastle, United Kingdom27d ago
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Validation/Verification (UVM, Coverage, Agentic), Staff Engineer INR 2000K-2372KAI Assisted Verification | Code Coverage | Coverage analysis | Debugging | Functional CoverageSenior-level Full TimeHyderabad, India28d ago
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Silicon Design Verification Engineer, Quantum AI USD 138K-198KARM | C-based testing | Chip verification | Constrained random | Constrained random verificationMid-level Full TimeMountain View, CA, USA; Goleta, CA, …1mo ago