Technical Lead Manager, Machine Learning, Memory Subsystem Design
Tasks
- Collaborate with cross-functional hardware teams
- Develop DRAM subsystem design and DV plans
- Drive design methodology process and quality improvements
- Interface with DRAM manufacturers for subsystem design and validation
- Interface with third party IP providers for memory components
- Lead and mentor memory subsystem design and verification teams
Perks/Benefits
- N/A
Skills/Tech-stack
DRAM | Design for test | Design verification | HBM | IP integration | Memory controller | Memory physical layer | Packaging | Physical Design | Physical layer | Power Integrity | RTL design | Signal Integrity | Silicon engineering | Silicon validation | Verification models
Education
Regions
Countries
States
Cities
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